Electronic circuits are becoming increasingly complex, using powerful processors, and implementing refined data management and control mechanisms notably (parallelism, pipelines, etc.), allowing still higher calculation power. Their architectures are complex, with a plurality of buses: a local bus to which the processor or processors and their main memories are directly connected, and in certain cases with cache memory controllers; and one or more expansion buses which make it possible to add input and/or output functionalities, notably additional memory cards, graphical functionalities, serial links, local networks etc. The local bus is then connected to the controllers of the various expansion buses. Various bus standards are used, generally corresponding to specific functions. Among the well known standards may be cited, the PCI (parallel) or PCI Express (serial), and USB expansion buses, for which corresponding connectors are commonly provided on the mother boards of the electronic circuits, for connecting specialized cards or additional memory cards thereto.
These architectures thus comprise various memory resources accessible to the various operators through appropriate data interfaces. These memory resources thus form a shared memory space which typically groups together: memory areas on the local or host bus, and on the expansion buses, accessible through the interface or the corresponding controller. The memories of this shared memory space will be for example random-access memories of SDRAM type or of any other type (ZBT “Zero Bus Turnaround”, DDR “Double Data Rate”, QDR “Quadruple Data Rate”, etc.) situated on the local bus or else made remote via a PCI bus, or programmable memories of flash EPROM type for example (USB bus), or other etc., and are read and/or write accessible.
As regards the various data transfer operators, they can be synchronous or asynchronous. They possess inherent work memory resources (registers, buffer memory), for temporarily storing the data exchanged, control information which defines the mode of operation of the interface (for example, direction of transfer: input/output, mode of transfer: interruption/polling), and state information, typically recorded in state registers, which advise notably as to whether transmission errors have occurred, and which are consulted by the processor. The operators can access the various common or shared memory areas of the electronic circuit. These operators can be software routines executed by the processor or services for transferring data blocks into memory or to communication networks, programmable automatons for transferring data blocks by Direct Memory Access (DMA), communication link controllers, such as serial or parallel link (UART) controllers, network controllers etc. the list does not presume to be exhaustive.
In these complex electronic circuits, accesses follow data paths comprising the various data interfaces, or controllers, through which the operators can read access and/or write access a given memory area. The various operators can act in a concurrent manner, requiring arbitrations on the access requests, which can be of various types. Notably the requests can be made according to a mode of transfer by polling or by interruption; and the structures of the data can vary according to the interfaces: byte (8 bits), word (16 bits), or other formats (24, 32 bits, etc.).
With the increasing complexity of these electronic circuits, the requirements as regards verifying the operation of these circuits have also grown, as has the difficulty of carrying out this verification in a satisfactory manner.
These verifications are notably very significant involving as they do circuits associated with security functions, such as onboard circuits embedded in aircraft: it is necessary to be able to certify their proper operation. Now, the asynchronous and concurrent processes which take place in these circuits give rise to many critical situations requiring arbitrations. It is necessary to be able to be certain that these situations and their arbitrations do not lead to any malfunction of the electronic circuit, in any circumstances. Stated otherwise, it is necessary to be able to verify correct operation in all possible situations.
According to a conventional approach, the test for verifying an electronic circuit ought to consist in reproducing all possible operating situations, and in verifying that for each of these situations, what is taking place is indeed what is expected for the situation considered. Such a test follows a systematic reasoned approach based on unit tests.
Such an approach encounters its limits in complex electronic circuits, on account of the multiplicity of situations to be envisaged and of the difficulty in envisaging them all, notably: multiplicity of resources, data paths, operators; concurrent behaviours of the various operators in accessing the memory resources, which involve arbitrations; pluralities of asynchronous clocks co-existing on the same circuit.
The latter feature is very penalizing in respect of the systematic reasoned approach based on unit testing since:                the combinatorial complexity resulting from the phase relations between the asynchronous clocks is tied to a continuous and no longer discrete physical phenomenon, thereby involving an uncountable quantity of different situations,        the respective phase of the asynchronous clocks is generally not controllable.        
At the same time, verification of the proper operation of the electronic circuits defined for carrying out critical functions is further complicated by the use of so-called COTS components, as opposed to components designed specifically for the application, that are necessarily more expensive. The use of COTS components makes it possible to meet the pressing demand from the market to reduce costs. On the other hand, it requires that the verifications performed be particularly effective in testing the behaviour of these components in critical situations, to alleviate the lack of complete design data on these COTS components.
Finally, recourse to external test toolkits to verify the data sent over the external communication links (serial links, networks, etc.) is a complex solution to implement notably in respect of the synchronization aspects.